Page 72 - Vol.13
P. 72

New
             Vision
             新象新知





                                                                           Weakness and
                                                                           Strength



                                                                                 a s e d  on  c on s e r va t i ve
                                                                                 estimation, even by shot or
                                                                           Bscan process cannot provide
                                                                           double throughput capability, the die
                                                                           cost saving still can reach around 20%
                                                                           in comparison with same technology
                                                                           node in 300mm production.

                                                                           Silicon wafers are made by CZ method
                                                                           (Czochralski  method),  followed
                                                                           300mm’s, in 450mm era. Fig.2 The main
                  Fuel In ow                          Depleted Fuel
                  (Glucose)                           Out ow               issue is the center sag level worse than
                                                      (Gluconolactone)
                                                                           300mm’s. If the sag level needs to keep
                                     Anode
                               (High-Surface-Area Platinum)  2e            as 300mm’s level, the wafer thickness
                                   Glucose Oxidation
                                            +
                               C H  O +H O → C H  O +2H +2e   Electrons are  will reach 1744um, far thicker than
                                                       Forced Through an
                                 Separetor Membrane     External Load      current standard 925 +/- 25um. [2] The
                                (Cation-Selective Na on)
                             2H +        +            ∆G =  2.51×10  J mol     potential impacts are wafer handling
                                Only Positive lons (H  but not e  )  U  = 1.30 V
                                Can Flow from Anode to Cathode
                                  Through the Separator                    and the silicon defects appearance
                                                       Electrons Recombine
                                     Cathode          with Hydrogen lons and  after high-temperature thermal
                              (Single-Walled Carbon Nanotubes)  Oxygen at Cathode  treatments. The other challenge is the
                                 Reduction of Oxygen to Water  H O   to form Water
                                      +
                                 ½O + 2H  + 2e  → H O                      silicon ingot might be hardly to reach
                             ½O
                  Oxidant In ow                                            the same length like 300mm’s. Shorter
                  (Oxygen)
                                                                           ingot length, thicker wafer and longer
                  Source. Rapoport BI, Kedzierski JT, Sarpeshkar R (2012) A Glucose Fuel Cell for   crystallization and cooling time
                   Implantable Brain–Machine Interfaces. PLoS ONE 7(6): e38436.
                                                                           indicate the cost reduction will take
                  Fig.1  Power Extraction from Cerebrospinal Fluid by an Implantable   more innovations and longer learning
                  Glucose Fuel Cell.
                                                                           curve to reach.
               generate electricity as bioimplantable power sources. Fig.1 [1]   This industry has got a consensus
               This indicates ultra-low power chips or micro-devices can be   on making a standard to remove
               implanted in human body and operated in a very long period   wafer notch, which is replaced by 3
               time without changing battery because this kind of glucose fuel   wafer back-side fiducial marks away
               cell can support electricity successfully.                  from wafer bevel 1.5mm. It is not so
                                                                           complex to set up a brand new process
               Those ultra-low power consumption and high computing        flow for notchless wafer production,
               performance devices will dominate the potential market
               demands in the coming decade. Beside of mobile phones, for   just adjusting few steps and sequence.
               example, new devices for wearable technology are soaring up   The benefits cover almost all kind
               in wider and wider applications. This stands for more advanced   of processes, mainly on uniformity
               technology nodes which will be required soon with higher and   improvements, and the hardware
               higher die cost and more and more sophisticated manufacturing   design of process tools can be more
               difficulties.                                               easier without a dedicated care on the
                                                                           notch area. Currently only two module
               450mm era brings an opportunity to lower the cost and technical   need to design new solutions to meet
               barrier by new design chamber, IT technology and advanced   notchless wafer characteristics. The
               process control. In 90nm technology node, the mask layers   first one is the wafer orientator or
               are below forty, but it will become around seventies in 10nm   aligner. Since current wafer sorters
               technology node. It seems impossible to drive the ultra-low   have applied image technologies to
               power application become poplar without aggressive die cost   recognize characters or patterns,
               saving and more output production.                          therefore just a change from a pure




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